Abstract
With the development of wide-bandgap (WBG) power semiconductor technology, such as silicon carbide (SiC) and gallium nitride (GaN), the technology of power converters with high efficiency and high-power density is rapidly developing. However, due to the high rate-of-rise of voltage (dv/dt) and of current (di/dt), compared to conventional Si-based power semiconductor devices, the reliability of the device is greatly affected by the parasitic inductance component in the switching loop. In this paper, we propose a power loop analysis method based on lumped parameter modeling of a power circuit board with a wide conduction area for WBG power semiconductors. The proposed analysis technique is modeled based on lumped parameters, so that power loops with various current paths can be analyzed; thus, the analysis is intuitive, easy to apply and realizes dynamic power loop analysis. Through the proposed analysis technique, it is possible to derive the effective parasitic inductance component for the main points in the power circuit board. The effectiveness of the lumped parameter model is verified through PSpice and Ansys Q3D simulation results.
Highlights
Power semiconductor devices such as MOSFETs and IGBTs are applied to various power electronics applications as key devices in power converters
Power electronics is a core technology applied to various power levels, from low-power fields of less than 1 kW to high-power fields of hundreds of kW
WBG devices are significantly affected by parasitic inductance, compared to conventional power semiconductor devices, between switching transitions due to their large rate-of-rise of voltage and of current [9]
Summary
Power semiconductor devices such as MOSFETs and IGBTs are applied to various power electronics applications as key devices in power converters. To reduce parasitic inductance, it is important to analyze inductances in the dynamic power loop considering the current distribution for each switching transient [14,15,16,17]. To consider various current paths between main elements in a power circuit having a wide current conduction area, the effective parasitic inductance is extracted by selecting multiple points in which a current can flow. The proposed power loop analysis technique analyzes the dynamic power loop formed during switching, applies FEM, that extracts the parasitic inductance between main devices using Ansys Q3D. To consider various current paths between main elements in a power circuit having a wide current conduction area, the effective parasitic inductance is extracted by selecting multiple points in wh iocfh14a current can flow.
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