Abstract
This paper presents the requirements for the Design for Manufacturability (DFM) checks such as lithography, and Chemical and Mechanical Polishing (CMP) at 28nm technology node, and the need to perform these DFM checks, early in the design phase and with minimum overhead. As a result, this reduces the risk of uncovering some DFM issues at the design tape out time when the changes in a design become expensive. Because IP blocks can be targeted to multiple designs, it is a key requirement that the lithography and CMP checks are accurate and designer-friendly and are easily applied at block-level. This paper describes the block-based methodology that allows the IP designers to perform quickly a comprehensive DFM analysis, including lithography and long-range CMP effects. This paper also explains the integration of the DFM checks into the design flow and correlation results between the block and chip-level checks.
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