Key Process steps for high reliable SiOCH low-k dielectrics for the sub 45nm technology nodes

Abstract

The introduction of SiOCH low-k dielectrics in copper interconnects associated to the reduction of the critical dimensions in advanced technology nodes is becoming a major reliability concern. The interconnect realization requires a consequent number of critical process steps [1]. Since porous low-k dielectrics are used as Inter-Metal Dielectric (IMD) each process step can be a source of degradation for the dielectric. This paper describes critical process steps influencing the low-k reliability. All the processes affecting the dielectric's interfaces are also evidenced to degrade the low-k interconnect robustness. Some process examples as the direct chemical and mechanical polishing (CMP), the slurry chemistry and the TaN/Ta barrier etching are details in this paper. Moreover, some process options are given to strongly improve low-k dielectric reliability without degradation of its electrical performances.