<title>Development of consolidated in-situ metallization processes for enhanced productivity</title>

Abstract

Backend metallization processes routinely consist of three separate steps when metallic barrier layers are sputtered: (1) deposition of the primary, conducting metal layer, (2) removal from the deposition system, and (3) deposition of a capping layer of a different metal, usually a metallic anti-reflective (ARC) coating. Physical sputtering systems sometimes are not configured to deposit the metal layers sequentially (insitu) without removal from the system, even though these modern tools have multiple chambers. This paper details how different metallization processes were consolidated to eliminate the air break between the primary conducting layer, typically Al or Cu, and the capping layers. This paper details the motivation, characterization, development, and electrical results of these new insitu processes for separate technologies on an Applied Materials Endura 5500 PVD. The motivation for backend process consolidation consisted of significant cycle time reduction, reduced cost of ownership across multiple tools, and reduced chance of depositing wrong capping layers. Wafer scrap risk and process integration is detailed for developing the insitu depositions for the A1CuW/TiN ARC stack. Optimization and characterization of the multiple step A1CuW deposition has been detailed previously [1] and is used as basis for this work. The concerns for both metal 1 and metal 2 A1CuW layers are described in addition to possible impact on existing photolithography and metal etch processes corresponding to these metal layers. Results show no significant difference in the critical dimensions after develop and after metal etch on both metal layers for the insitu AICuW ITiN ARC process even though there was a 32% increase in the insitu A1CuW ITiN stack reflectivity compared to the standard stack A1CuW ITiN ARC process. Data is presented showing throughput increased by close to 20% using the insitu AICuW ITiN ARC process compared to the standard process for both metal stack layers. Cycle time reduction and reduced cost of equipment ownership was achieved without any decrease in wafer die probe yield or significant change to existing photolithography and etch processes.