Low-Voltage Swing Clock Distribution

Abstract

The clock network can consume up to 50% microprocessor power based on the experimental data shown in Figure 1-2. The clock gating technique is often used to reduce the wasted power in the clock distribution. This technique adds a stop clock signal for the clock buffer to gate the clock when the clock is not needed for a portion of the clock distribution network. This chapter describes a clock distribution system with low voltage swing clock signals [34]. While the system has an operating voltage generally used throughout the system, at least one of the global clock signal and the local clock signal is a small swing clock signal that has a voltage swing substantially less than the operating voltage of the system. Section 8.1 presents a 1/2Vdd swing local clock distribution scheme. Section 8.2 presents the low voltage swing global clock distribution scheme. Section 8.3 provides a summary to this chapter.