Dual-edge triggered level converting flip-flops

Abstract

Level converting flip-flops are critical elements in dual-V/sub DD/ design for level conversion at the interface from low supply to high supply regions. Level converting flip-flops also provide energy savings on the clock distribution network by using low-swing clock signals. We propose dual-edge triggered level converting flip-flops that provide data sampling and level converting functions at both rising and falling edges of a low-swing clock. Adding the dual-edge triggering feature to level converting flip-flops, the clock frequency can be reduced by half, resulting in 50% power savings on the clock tree in addition to the savings due to low voltage swing clock. Moreover, the proposed flip-flops outperform the existing level converting flip-flops in terms of performance. The dual-edge triggering capability is achieved by using a dual pulse clock generator that generates short pulses at both rising and falling edges of the clock. Based on simulation results in a 0.25 /spl mu/m CMOS technology, the proposed flip-flops exhibit up to 68% delay reduction as compared to existing level converting flip-flops.