Abstract
The electrical performance of junctionless transistors (JLTs) with planar structures was investigated under low-temperature and compared to that of the traditional inversion-mode (IM) transistors. The low-field mobility (μ0) of JLT devices was found to be limited by phonon and neutral defects scattering mechanisms for long gate lengths, whereas scattering by charged and neutral defects mostly dominated for short gate lengths, likely due to the defects induced by the source/drain (S/D) implantation added in the process. Moreover, the temperature dependence of flat-band voltage (Vfb), threshold voltage (Vth) and subthreshold swing (S) of JLT devices was also discussed.
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