Low-Power/Low-Voltage analog front-end for LF passive RFID tag systems

Abstract

Radio Frequency Identification (RFID) systems are widely used in a variety of tracking, security and tagging applications. In this context, passive low-frequency (LF) RFID systems have a large installed base, mostly used for animal tagging and supply chain applications. This paper presents a Low-Power/Low-Voltage analog front-end architecture (AFE) for such RFID systems, discussing the design and technology issues related with standard deep-submicron CMOS processes. The AFE converts the incoming AC power (134.2kHz) into DC power (1.2V) and internal references (570mV and 5nA) using low power design techniques in order to increase overall performance. An improved rectifier structure was designed using a half-wave voltage doubler topology with self-bias feedback, providing efficient rectification. A shunt regulator stage was proposed as a fundamental part of the AFE architecture, since it keeps the rectified voltage at 3V and generates the signal for demodulation for all power levels and process variations. Finally, a low-power/low-voltage PMU architecture was designed, containing a new reference voltage approach based on two NMOS transistors with different Vt's consuming 170nA (startup circuit included); a 5nA reference current based in SCM (Self Cascode Mosfet) structures; and a dual-mode capacitor-less voltage regulator consuming 400nA. In order to increase the yield of the system, the VI reference block passed through a yield optimization using the tool WiCkeD, which showed a block yield increase of 71.66%.