Low-power implementations of DSP through operand isolation and clock gating

Abstract

The advent of implantable devices such as digital cochlea has made low power circuit design an increasingly important research area. In this paper, we utilize the operand isolation to save power dissipation in data-path by reducing unnecessary switching activity and clock gating to reduce redundant power dissipation in registers of our DSP which is used for implantable digital cochlea. Experimental result from running application program on our design shows 27.64% reduction in dynamic switching power with no increase in critical path delay and only 2.10% area overhead.