Low-power high-speed ECL circuit with 0.5- mu m rule and 30-GHz f/sub T/ technology

Abstract

Optimized self-aligned transistors for low-power ECL (emitter-coupled-logic) circuit applications are discussed. The ECL circuit was fabricated using a 0.5- mu m rule and a 28-GHz f/sub T/ technology and evaluated in terms of the propagation delay time of ring oscillators and a 1/8 static divider. The analysis of the circuit, the process design, and the npn transistor structure are discussed. A 39-ps/1.6-mW ECL circuit and a 12.5-GHz 1/8 static divider were obtained. >