Sub-15 ps gate delay with new AC-coupled active pull-down ECL circuit

Abstract

An ECL (emitter coupled logic) circuit with an AC-coupled active pull-down emitter follower configuration is described. An unloaded ring oscillator gate delay of 13.2 ps has been achieved at 6.2 mW, in a 50 GHz-f/sub T/ ion-implanted silicon bipolar technology. This circuit could be useful as an internal gate operating at low-power and as an I/O gate to drive a large capacitive load at high-power. In both cases, this circuit offers superior power-delay performance compared to conventional ECL circuits. >