Low-Power High-Performance Multitransform Architecture Using Run-Time Reconfigurable Adder for FPGA and ASIC Implementation

Abstract

The multistandard transform (MST) architecture for MPEG-1/2/4, H.264 and VC-1 using common sharing distributed arithmetic (CSDA) is more popular in multimedia communications. The CSDA and multitransform architecture have more number of 12-bit and 16-bit adders. In real-time computation, more redundant input data present in the most significant bit (MSB) part. So, in this paper, a detector logic circuit is developed to distinguish unwanted and informative portion of the input data. Then, the detector logic circuit-based run-time reconfigurable adder is designed. The detector result is used to disable the unnecessary computation block within the 12-bit adder, whenever non-informative data present in the input side of the adder. Therefore, it reduces the signal-level changes in the logic gate circuits and proportionally the power consumption becomes less. This improved architecture design is used in the 2D CSDA-MST core to analyse computation speed and power consumption. The proposed adder is evaluated with 12-bit and 16-bit input length. The calculated result shows that 21.6 and 16.25% of active logic gate reduce for 12-bit and 16-bit adder, respectively. Also, synthesized result of the proposed adder-based 2D CSDA-MST core is compared with spurious power suppression technique (SPST) adder-based 2D CSDA-MST core. The major advantage of the proposed adder is less power consumption with miniature overhead of the area. So, the proposed run-time configurable adder-based 2D CSDA-MST core is suitable for low-power and high-speed multimedia applications.