Low-power high-linearity 0.13-µm CMOS WCDMA receiver front-end

Abstract

This paper presents a low-power high-linearity variable gain WCDMA receiver (Rx) front-end. The Rx front-end consists of a variable gain low noise amplifier (LNA) and a folded double balanced mixer. By enhancing the substrate resistance of a common gate transistor of LNA along with adopting multiple-gate technique, the linearity is significantly improved. Multiple-gate transistor technique is also adopted in g m stage of the I/Q mixer to improve the linearity. The receiver is designed based on direct conversion architecture in 0.13-µm CMOS process from 1.2 V supply. The high gain mode shows 37dB of voltage gain with 1.16dB of NF. The Rx front-end achieves −4.2dBm of IIP3 while consumes 8.9mW. The active size is 600 × 380 µm2.