Abstract
In this paper we presented a new 13T full adder design based on hybrid --CMOS logic design style. Adders are one of the most basic building blocks in digital components present in the Arithmetic Logic Unit (ALU). The performance of an adder have a significant impact on the overall performance of a digital system. The new design is compared with some existing designs for power consumption, delay, PDP at various frequencies viz 10 MHz, 200 MHz and 1 GHz. the simulations are carried out on Cadence Virtuoso at 180nm CMOS technology and the simulation results are analyzed to verify the superiority of the proposed design over the existing designs. Maximum saving of power delay product is at low frequency by proposed circuit is 96.8% with respect to C-CMOS and significant improvement is observed at other frequencies also. The power consumption increases at a slow rate in comparison to other adders with increase in frequency.
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