Abstract
The cost-effective realization of forward/inverse Fast Fourier Transform (FFT/IFFT) in Digital Subscriber Line (DSL) systems is addressed in the paper. A processor based on a FFT/IFFT cascade architecture plus pre/postprocessing stages is discussed and characterized from the high-level choices down to gate-level synthesis. The effects of supply voltage scaling on power consumption and circuit performance are examined, as well as the use of different target technologies. Low-power design techniques, based on clock gating and data driven switching activity reduction, further decrease the energy consumption. Synthesis results in a 0.18 /spl mu/m CMOS technology show that the processor is suitable for real-time modulation/demodulation in scalable VDSL systems with a power consumption of few tens of mW.
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