Low-Power and High-Speed Approximate Multiplier Design with a Tree Compressor

Abstract

Many applications, such as image signal processing, has an inherent tolerance for insignificant inaccuracies. Multipliers are key arithmetic functions for many error-tolerant applications. Approximate multipliers are considered an efficient technique to trade off energy relative to performance and accuracy. We propose two approximate multiplier designs that demonstrate lower power consumption and shorter critical path delay than the conventional multiplier by employing an approximate tree compressor. The proposed compressor halves the height of the partial product tree and generates a vector to recover accuracy. Compared to the conventional Wallace tree multiplier, one of the proposed 8-bit approximate multipliers reduces power consumption and critical path delay by 59.9% and 36.3%, respectively. Furthermore, with 0.28% normalized mean error distance, the silicon area required to implement the multiplier is reduced by 50.1%. The proposed approximate multiplier designs outperform previous multipliers relative to power consumption, critical path delay, and design area.