Low-Power and Area-Efficient Design of Higher-Order Floating-Point Multipliers Using Vedic Mathematics

Abstract

Floating-point arithmetic units form the backbone of the state-of-the-art digital signal processing algorithms. Low power and area efficient design is always a key requirement for applications that use these algorithms. This requirement is more relevant for computationally intensive jobs that use higher-order multipliers. This paper attempts to study the possibility of addressing this issue using vedic arithmetic based floating-point unit. Vedic mathematics is an ancient Indian mathematics system that has come back to prominence in the last century. In this paper, we design a IEEE 754 single precision floating-point multiplier with the integer multiplication being carried out in a vedic mathematics style using different sutras. Nikhilam and Urdhva Tiryagbhyam sutras and their combination are used to design the same. This implementation is compared with conventional implementations using Booth and array multipliers. The designs are simulated using Verilog and synthesized using gpdk 90 nm technology. The results show that vedic multiplier based design gives competing results for multipliers of larger sizes. Low power and area efficient design is achieved for higher order multipliers when the design is based on the combination of Nikhilam and Urdhva Tiryagbhyam sutras. Thus for DSP applications using large multipliers, it is envisaged this approach of vedic multiplier design would lead to more efficient system implementations.