Low-frequency noise and random telegraph signals in 0.35 μm silicon CMOS devices

Abstract

A detailed investigation of the low frequency noise in Si MOS devices issued from a 0.35 μm CMOS technology is conducted. The normalized drain current noise WLSid/Id2 has been systematically measured at a fixed frequency (10 Hz) and constant normalized drain current. It is found that, for large area devices (≥7–10 μm2), the sample‐to‐sample noise level variation lies around a factor of 2–3, while, for the smallest devices (0.1–0.3 μm2), the sample‐to‐sample noise level variation can exceed 3 decades. In large area devices, the 1/f noise can easily be described by a classical carrier number fluctuation model using the concept of dynamic flat band voltage. In the case of intermediate or small areas, a multi‐RTS component scheme has to be employed.