Low-Cost and High-Throughput Hardware Accelerator for Deblocking Filter in HEVC

Abstract

This paper proposes a low-cost and high-throughput hardware accelerator for the deblocking filter in the encoder and decoder of high-efficiency video coding (HEVC). The total image is split into CTUs (coding tree units) of size 64 × 64 pixels each, which are further divided into 32 × 32 blocks and individually processed. Parallelism is simultaneously applied in this design to filter two luma edges and one chroma edge. In order to minimize the area utilization, the same filter is used for filtering both horizontal and vertical edges. The proposed architecture takes 36 clock cycles to process a 32 × 32 block of the image. The design is implemented in Virtex-6 and Zybo FPGA boards and also in the Cadence tool. The pipelining techniques are used effectively at various levels to provide a high-throughput design, which supports the deblocking of a 16 K UHD (ultra-high definition) video at 134 frames per second (fps).