Low Voltage 7T SRAM cell in 32nm CMOS Technology Node

Abstract

The escalating demand for low power portable devices has increased the pressure on shrinking device technology to operate at low supply voltages. But at small feature size and low supply voltage the performance of SRAM – a major component of every device - degrades considerably. In this paper a novel 7T SRAM cell is proposed, which has improved static and dynamic performance matrix at supply voltage as low as 300mV. The proposed bit cell has single ended write and double ended read operation. The proposed cell improves the read static noise margin, hold static noise margin and write margin by 20%, 24% and 10% respectively when compared with conventional 7T bit cell structure. In comparison to 6T conventional structure the proposed cell has 76% improvement in hold noise margin and 26% improved write margin. The conventional 6T SRAM bit cell fails to perform read operation below 600 mV, whereas the proposed cell maintains a read static noise margin of 47 mV at 300mV supply voltage. The proposed cell is simulated for 32nm technology node.