Low temperature plasma enhanced CVD of highly conductive single crystalline and polycrystalline silicon materials

Abstract

Abstract The technique of plasma enhanced CVD at temperatures as low as 200–350° C can successfully be used to deposit highly conductive silicon layers with preservation of the crystalline structure of the underlying substrate or film (single- or polycrystalline). The influence of different substrate preparation and deposition conditions and annealing steps afterwards is carefully studied. Two applications have been realized: bipolar transistors with epitaxial emitter resulting in comparable current gains as homojunction transistors and polysilicon thin film transistors with plasma deposited highly conductive source and drain regions resulting in channel mobilities of 16.5 cm 2 /V·s.