Low temperature micro-bumping assembly technology for 3D integration

Abstract

3DIC integration has been well know as the next generation of semiconductor technology with the advantages of small form factor, high performance, low power consumption, high density integration, etc. The stacked assembly is one of the key enabling technologies to perform 3D integration. One popular approach to achieve intrinsic metal interconnect is stacked bonding by lead-free solder bumps. With the demand of high performance and high density applications, the development of fine pitch micro-bumps becomes more and more important in order to meet the requirements of low profile, light weight, and high pin counts for 3DIC integration applications There are three major important steps in assembly technologies for 3DIC integration: 1) micro-bumping wafer; 2) fabricating the TSV (through-silicon via)/RDL (redistribution layer)/IPD (integrated passive device) interposer/chip wafer with UBMs on its top-side and either ordinary solder bumps or UBMs at its bottom-side (temporary bonding and de-bonding the wafer to a supporting wafer is usually required); and 3) dicing the wafer into individual chip and bond it to the interposer/chip wafer (C2W) bonding or wafer to wafer (W2W) bonding. In this study, ultra fine pitch In lead-free solder micro-bumps are investigated. Emphasis is placed on wafer bumping, assembly, and reliability of micro-bumps for 3DIC integration applications. In this work, the optimum bonding condition is determined and the cross sections are characterized with SEM.