Low-temperature characterization and modeling of advanced GeOI pMOSFETs: Mobility mechanisms and origin of the parasitic conduction

Abstract

We present the fabrication and characterization of Fully-Depleted pMOSFETs processed on ultra-thin GeOI (Germanium-On-Insulator) wafers obtained by the Enrichment technique. The fabrication procedures for wafers and pMOSFETs are detailed. The influence of temperature (77K<T<300K) on front (Ge-high-κ) and back (Ge–SiO2) channel properties, such as the hole mobility, the threshold voltage and the substhreshold swing, is reported. Very high values of hole mobility have been measured (350 and 595cm2V−1s−1 at 300K and 77K, respectively). The carrier scattering mechanisms are revealed from the temperature-dependent hole mobility. The role of the interface defects and residual body doping on the parasitic conduction is clarified based on the threshold voltage shift measured at low temperature. An appropriate VT(T) model, providing relevant information on the Dit distribution in the Ge band gap, is proposed.