Abstract
For the lowest resistance, it is required to have the epitaxial silicon contact between the silicon plug and the substrate and good step coverage at the high aspect-ratio contact holes, simultaneously. In this work, a double polysilicon (DPS) deposition technique was proposed for the requirements. The first, thin silicon layer is deposited in a single-wafer process chamber with an in-situ H2-RTP (rapid thermal process) treatment for the epitaxial contact, and the second silicon layer is formed in a batch-type furnace for good step coverage. From chain resistance, Kelvin Rc, and current-voltage (I–V) measurement, the DPS process meets both low resistance and good uniformity, so that it suggests a breakthrough in the small-sized, semiconductor device application.
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