Low Power SOT-MRAM Cell Configuration For Dual Write Operation

Abstract

Due to the leakage power of CMOS-based memory, Nonvolatile magnetic memory is considered a strong candidate to replace the CMOS-based memory. Spin transfer torque magnetic random access memory (STT-MRAM) is one of the most promising candidates, but it still has many shortcomings related to the write operation. Compared to STT-MRAM, spin orbit torque magnetic random access memory (SOT-MRAM) is the next generation of nonvolatile magnetic memory because of its relatively good performance and low power. Although SOT-MRAM has various advantages over STT-MRAM, a significant reduction in write power is required to meet the power level of CMOS-based memory. In this paper, we present a low power SOT-MRAM cell configuration using the dual write operation. By writing on two cells simultaneously, write energy can be reduced depending on data patterns. Compared to the conventional 2T-1MTJ SOT-MRAM, the proposed SOT-MRAM cell with the dual write scheme reduces the write energy by 26.3% on average.