Low-Power Regulated Cascode CMOS Transimpedance Amplifier with Local Feedback Circuit

Yasuhiro Takahashi,Makoto Nakamura,Toshiyuki Inoue,Akira Tsuchiya,Keiji Kishine,Daisuke Ito

doi:10.3390/electronics11060854

Yasuhiro Takahashi, Makoto Nakamura + Show 4 more

Open Access

https://doi.org/10.3390/electronics11060854

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Journal: Electronics	Publication Date: Mar 9, 2022
Citations: 5	License type: CC BY 4.0

Affiliation: Gifu University, University of Shiga Prefecture

Abstract

In this paper, we propose a multistage transimpedance amplifier (TIA) based on the local negative feedback technique. Compared with the conventional global-feedback technique, the proposed TIA has the advantages of a wider bandwidth, and lower power dissipation. The schematic and characteristics of the proposed TIA circuit are described. Moreover, the proposed TIA employs inductive peaking to increase bandwidth. The TIA is implemented using a 65 nm complementary metal oxide semiconductor (CMOS) technology and consumes 23.9 mW with a supply voltage of 1.0 V. Using a back-annotated simulation, we obtained the following characteristics: a gain of 46 dBΩ and −3 dB frequency of 11.4 GHz. TIA occupies an area of 366 μm × 225 μm.

Highlights

A transimpedance amplifier (TIA) is a very important building block for current optoelectronic communication systems, e.g., optical receivers for optical frequency combs [1–3], localized machine-to-machine communication systems [4,5], or optical metro long-haul fiber communication systems [6–8]
The proposed TIA was designed for long-haul fiber communications using the InP heterojunction bipolar transistor (HBT) process; when designing a complete optical receiver system, a digital part of the chip, such as field-programmable gate array or application-specific integrated circuit, is needed
This paper proposes an regulated cascode (RGC) type TIA based on a local feedback technique

Summary

Introduction

A transimpedance amplifier (TIA) is a very important building block for current optoelectronic communication systems, e.g., optical receivers for optical frequency combs [1–3], localized machine-to-machine (i.e., short distance) communication systems [4,5], or optical metro long-haul fiber communication systems [6–8]. TIAs can be fabricated using many different transistor processes, but CMOS process offers the ability of direct integration with digital logic circuits. This integration is vital, as the challenges encountered by optical heterodyne receivers include cost (e.g., chip size and power consumption). The proposed TIA was designed for long-haul fiber communications using the InP HBT process; when designing a complete optical receiver system, a digital part of the chip, such as field-programmable gate array or application-specific integrated circuit, is needed.

Analysis of Circuit Topology

Post-Layout Simulation Results

50 TIA core PA Buffer

Conclusions