Abstract
This paper describes a project undertaken to explore reconfigurable computing as a means to achieve high-throughput, low-power on-board computing for spacecraft. The solution consists of a reconfigurable data processor chip, a reconfigurable memory module, reconfigurable interconnect, and dynamic power management. The reconfigurable processor chip was fabricated in a 0.25µ bulk CMOS process using a radiation-hard-by-design standard cell library. Two challenge algorithms were demonstrated in hardware, and a dozen others in software simulation. It was shown to achieve up to 3 giga- operations/second-watt. This architecture is well-suited to future generations of ultra-low-power, low-voltage processors and memories, as the extensibility offsets the loss in throughput due to low-voltage
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