RISP Configuration Overhead Optimization Using an Efficient Configuration Unit

Abstract

Reconfigurable computing is the next generation approach to compute the algorithms with as much high speed as that of application specific integrated circuits along with the as much flexibility as that of programmable processors. The reconfigurable instruction set processors being most prominent execution platforms for reconfigurable computing have been evolved through many design alternatives. The evolution has explored that the execution performance of a typical reconfigurable processor is greatly dependant on the basic design of its configuration unit. Configuration updation of reconfigurable processor is the dynamically controlled by this unit and hence this unit plays a vital role in the performance enhancement of reconfigurable processor. In this research paper an efficient configuration unit design has been presented which has the capability of loading the most optimal configurations by making the maximum reusability of the existing configuration streams. The simulated results have shown that proposed configuration unit always demonstrates most optimal configuration overhead for reconfigurable processors and hence can be used in high speed reconfigurable instruction set processors.