Low power pulse triggered D-flip flops using MTCMOS and Self-controllable voltage level circuit

Abstract

Reducing power consumption is a crucial task for any circuits. Increased demand for portable devices with reduced power dissipation has put necessary traction to design low power circuits. Both explicit and implicit pulse triggered flip flops are designed. Multiple Threshold CMOS (MTCMOS) technique and Self-controllable voltage level (SVL) circuit are employed to reduce power consumption. All the circuits are designed in 45nm technology for 1 GHz frequency.