Development of a high stability, low standby power six-transistor CMOS SRAM employing a single power supply

Abstract

We developed and applied a new circuit, called the Self-controllable Voltage Level (SVL) circuit, not only to expand both write and read stabilities, but also to achieve a low stand-by power and data holding capability in a single low power supply, 90-nm, 2-kbit, six-transistor CMOS SRAM. The SVL circuit can adaptively lower and higher the wordline voltages for a read and write operation, respectively. It can also adaptively lower and higher the memory cell supply voltages for the write and hold operations, and read operation, respectively. A Si area overhead of the SVL circuit is only 1.383% of the conventional SRAM.