Low power process tolerant nano cache memory for military applications

Abstract

ABSTRACT Rapid growth in high-performance battery-powered computing applications, Internet of Things (IoT) and artificial intelligence (AI), has raised the need for low-power integrated circuits. Particularly in military applications, wireless sensor nodes are used to detect border intrusion, weapon attacks, biometric wearables, internet of battlefield things (IoBT), etc. The computing and security devices utilised by the soldiers are powered by batteries. To increase the life and performance of these devices, the integrated circuits (IC) used within these devices need careful design. Particularly, an appropriate memory needs more attention because the design of memory has a substantial impact on IC performance as it occupies most of the chip space. In this article, a novel 8T transistor low-power cache memory cell is proposed and simulations for nominal chirality and dual chirality are done using HSPICE-compatible CNFET (carbon nanotube field effect transistor) technology. The power consumption is minimized in dual chirality case than nominal chirality. But still the power saving percentage of the proposed cache memory cell remains good compared to conventional memory structures. Thus the proposed cache memory cell provides low power, delay and energy apart from being process tolerant, thus proving that it is compatible for warfare and military applications.