Hardware Design and Implementation of Multiagent MLP Regression for the Estimation of Gunshot Direction on IoBT Edge Gateway

Abstract

The advancements in the internet of things, artificial intelligence, and state-of-the-art computing techniques are the main pillars of the next generation defense technology. The internet of battlefield things (IoBT) with edge intelligence offers new opportunities for defense professionals for smart and effective military operations. The IoBT network connects soldiers by placing smart sensors on armors, weapons, body, and surroundings. This paper presents a novel edge intelligence based estimation of gunshot direction from the sensor-enabled glove for smart IoBT wearables. A multi-agent multi-layer perceptron (MA-MLP) and other regression models are developed and tested on the experimental dataset collected during this study. The MA-MLP model consists of two distinct MLP networks and a fusion block to estimate the gunshot direction. This paper demonstrates the effect of multiple subjects, sensor positions, and gun material on mean absolute error (MAE) of MA-MLP prediction. The software simulation results show that our proposed MA-MLP model has outperformed traditional machine learning techniques like linear regression, SVM and MLP with an MAE of 4.09°. Two different hardware designs i.e., intellectual property (IP) cores of the pre-trained MA-MLP model are implemented and tested on a field-programmable gate array (FPGA) for a system on a chip (SoC) based edge gateway. The first IP core requires 280 nanoseconds with a power consumption of 354 milliwatts while the second IP core requires 380 nanoseconds with 178 milliwatts power consumption per inference. Prediction accuracy of 97.48% with a reduction of throughput to 92.2% is achieved for both IP cores. This work is one of the first attempts to implement the FPGA-based edge intelligence for the IoBT wearables. The short computation time, low power consumption, small footprint, significant throughput reduction, desired accuracy, and processor offloading are achieved by both flexible hardware models designed explicitly for the edge intelligence.