Low power low jitter phase locked loop for high speed clock generation

Abstract

Low power consumption is always desired for any electronic products today. CMOS technology is the most common process to make integrated-circuits. The work focuses on the design and simulation of low jitter and low power CMOS PLL integrated circuits using 180nm CMOS technology. A current-controlled ring oscillator based on a single-ended rail-to-rail operational transconductance amplifier (OTA) and three simple CMOS inverters, is employed and tested in this work. The circuit uses less number of transistors and hence consumes low power compared to conventional oscillator circuits. Conventional static Phase Frequency Detector (PFD) has a wide dead zone (undetectable phase difference range), which results in increased jitter. The jitter caused by the large dead zone can be reduced by increasing the precision of the phase frequency detector. Any width of the dead-zone directly translates to jitter in the PLL which is an undesirable performance that must be avoided. To overcome the speed limitation and to reduce the dead zone, a new dynamic logic style PFD was designed and simulated. The designing of charge pump for getting faithful response is a difficult task because of mismatch in charging and discharging currents. The charge pump developed in this work employs an operational amplifier designed for reducing the error caused by high speed glitches in the transistor and mismatch between charging and discharging currents. A low noise charge-pump to achieve low phase jitter together with OTA based VCO, a PFD based on dynamic logic circuit, and a passive loop filter is integrated to obtain the Phase Locked Loop architecture. The simulation results of the PLL exhibits a working frequency range of 640 to 800 MHz and the utmost lock time of 6s. This frequency range renders the designed phase locked loop architecture that can be used as clock generator in microprocessors.