PFD with Dead zone based Low Power Modified Phase Lock Loop using AVLS Technique

Abstract

Phase lock loop (PLL) operates at higher frequency and due to the increased switching, the power consumed is high. The increase in demand of applications in communications systems has led to fully integrated, minimal power and high performance PLL. There is a demand for low power applications and hence various methods have been emerging. The power of the PLL has to be reduced and optimized by reducing the power of all the sub-blocks of PLL. Adaptive voltage level (AVLS) technique is incorporated in the circuit to reduce power consumption. The phase detector of the PLL is replaced with a phase frequency detector with dead zone which is used to reduce the power of the PLL. The number of transistors is also reduced thereby reducing the area of the PLL. Also MOSFETs are used for the design of loop filter. The circuits are realized using CMOS 180nm technology in Cadence Virtuoso and simulated using Cadence Spectre. Proposed modified PLL architecture's is compared w.r.t. reference PLL architectures at various frequencies. Proposed PLL architectures consumes very less power compared to reference PLL architectures even at higher frequency (>1 GHz).