Low Power, Low Chip Area, Digital Distance Calculation Circuit for Self-Organizing Neural Networks Realized in the CMOS Technology

Abstract

This paper presents a new distance calculation circuit (DCC) that in artificial neural networks is used to calculate distances between vectors of signals. The proposed circuit is a digital, fully parallel and asynchronous solution. The complexity of the circuit strongly depends on the type of the distance measure. Considering two popular measures i.e. the Euclidean (L2) and the Manhattan (L1) one, it is shown that in the L2 case the number of transistors is even ten times larger than in the L1 case. Investigations carried out on the system level show that the L1 measure is a good estimate of the L2 one. For the L1 measure, for an example case of 4 inputs, for 10 bits of resolution of the signals, the number of transistors is equal to c. 2500. As transistors of minimum sizes can be used, the chip area of a single DCC, if realized in the CMOS 180 nm technology, is less than 0.015 mm2.