Low Power, Low Chip Area, Programmable PID Controller Realized in the CMOS Technology

Abstract

The subject of the proposed paper is a novel, transistor level implementation (in the CMOS technology) of a programmable PID (proportional-integral-derivative) controller. In our work we focus on a discrete-time digital approach, as it facilities realization of a programmable structure which is more flexible. The novelty of the proposed solution relies on implementing the PID controller as a parallel and asynchronous structure, controlled by a simple 2-phases clock. Each of the P, I and D parts is realized as a separate channel with an own multi-bit multiplier, a summing circuit and a delay line (in the I and the D parts). The multiplier is realized as a binary tree circuit that works fully asynchronously. The implementation in the CMOS technology allows to obtain a small structure. For the input signals, and the coefficients of the PID controller encoded on 8-bits the total number of transistors does not exceed 13000. In the CMOS 180 nm technology the chip area approximately equals 0.15 mm2. Data rate is in this case even as high as 200–330 MHz, depending on the temperature and supply voltage, at very low power dissipation not exceeding 1 mW. Such a solution is suitable for various microsystems and embedded systems (used for example in automotive applications) in which small sizes and high data rate become very important features.