Low Power High Performance ROM Design on FPGA Using LVDCI I/O Standard

Abstract

In this work, we are using LVDCI I/O standard in energy efficient ROM design on FPGA. There is a 92% reduction in clock power, 50% reduction in signal power, 32-46% reduction in IO's power, and 25-27% reduction in total power, when we scale down frequency from 4.0GHz to 1.0GHz. There is no reduction in clock power and signal power, when we change I/O standard from LVDCI 25 to LVDCI 15, but there is reduction of 61-69% of IO's power and reduction of 16-18% in total power. This design is implemented on Virtex-5 FPGA using Verilog hardware description language and Xilinx ISE simulator. LVDCI 15, LVDCI 18, LVDCI 25, HSLVDCI 15 and HSLVDCI 18 are five different IO standard is in use to design energy efficient ROM. LV stands for Low Voltage, HS means High Speed and DCI means Digitally Control impedance.