Abstract
The development of a class-AB technique in two-step sampling switched currents (S/sup 2/I) is presented. The technique offers a significant improvement over the conventional class-A S/sup 2/I in terms of both linearity and a figure-of-merit combining speed, power consumption, and signal-to-noise ratio. In addition, it enables the S/sup 2/I scheme to operate at lower supply voltages responding to the demand for a supply reduction in modern digital CMOS processes. An experimental S/sup 2/I sample-and-hold circuit based on two parallel S/sup 2/I memories achieved better than -63 dB total harmonic distortion, 63.6 dB signal-to-noise ratio, and dissipated 1.45 mW at more than 120-MHz sampling rate and a supply voltage of 2.4 V. These indicate an overall improvement by a factor of about 2.9 in comparison with the test results obtained from the class-A S/sup 2/I sample-and-hold circuit designed to operate at exactly the same conditions.
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