A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs

Abstract

This paper presents the design of a high-speed CMOS sample-and-hold (S/H) circuit for pipelined analog-to-digital converters (ADCs). This S/H circuit employs a conventional switched-capacitor (SC) S/H and a built-in comparator to generate the mixed-mode sampled data output (which is represented both in analog and digital formation). Due to the mixed-mode sample-and-hold technique, this S/H circuit has a reduced output signal swing thus improves the speed and linearity compared to conventional S/H circuits. The aperture errors at high frequency are minimized by using time constants matching and digital error correction logic in pipelined ADCs. Designed in a 0.18mum CMOS technology, the proposed S/H circuit operates up to 200-MHz sampling with less than -53dB total harmonic distortion (THD) in the worst case corner simulation. The power consumption is less than 3.6-mW with 1.8-V supply voltage