Abstract
A new multiplication algorithm is introduced for the low-power implementation of digital filters on CMOS based digital signal processing systems. The algorithm decomposes individual coefficients into two less complex subcomponents. The decomposition, performed using a heuristic approach, divides a given coefficient such that a part is produced which can be implemented using a single shift operation, leaving another part with a reduced wordlength to be applied to the coefficient input of the hardware multiplier. This results in a significant reduction in the amount of switched capacitance and consequently power consumption. The authors describe the algorithm and present associated results, including the effects of overheads due to shift operations, showing up to 63% saving in power.
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