VLSI Implementation of 3-Parallel FIR Filters through Coefficient Symmetry Property and Fast FIR Algorithm

Abstract

In multirate digital signal processing systems, polyphase filters are frequently used. The challenges in multirate digital signal processing systems primarily relate to efficiently processing signals at different rates while maintaining high-quality output. These challenges include computational complexity, power consumption, and signal delay. The coefficient symmetry property plays a key role in systematically arranging of filter taps in symmetric manner to improve operating efficiency. With a major focus on using the coefficient symmetry characteristic, this paper addresses the VLSI implementation of traditional Type-1 polyphase FIR filters. Furthermore, this paper incorporated 3-parallel FIR filters especially for sequences with odd lengths in order to take full advantage of the coefficient symmetry characteristic. The Fast FIR Algorithm (FFA) method is used to increase overall efficiency. Furthermore, in order to achieve better performance, a modified FFA technique is introduced to enhance overall performance. The paper thoroughly investigates important VLSI factors, such as power consumption, utilization, and delay, and shows how, by utilizing coefficient symmetry and applying this modified FFA technique, filters that are optimized for both power consumption and area utilization are able to be implemented. The results illustrate a significant reduction in both area and power consumption, particularly for longer filters, attributed to the reduced number of multiplication operations inherent in the fast FIR algorithm approach. Additionally, image processing application using 3x3 FIR filter is executed.