Low Power Arithmetic Circuits in Feedthrough Dynamic CMOS Logic

Victor Navarro-Botello,Mike Dyer,Saeid Nooshabadi,Juan A Montiel-Nelson

doi:10.1109/mwscas.2006.382161

Low Power Arithmetic Circuits in Feedthrough Dynamic CMOS Logic

Victor Navarro-Botello, Mike Dyer + Show 2 more

https://doi.org/10.1109/mwscas.2006.382161

Copy DOI

Publication Date: Aug 1, 2006

Citations: 16

Affiliation: University of Las Palmas de Gran Canaria, UNSW Sydney

#Feedthrough Logic #Standard CMOS Technologies + Show 8 more

Abstract
Full-Text PDF
Similar Papers

Abstract

This paper presents the design of low power high performance arithmetic circuits using the feedthrough logic (FTL) [1] concept. Low power FTL arithmetic circuits provide for smaller propagation time delay (2.6 times), lower energy consumption (31%), and similar combined delay, power consumption, and active area product, when compared with the standard CMOS technologies.

Full Text