Low power and robust 7T dual-Vt SRAM circuit

Abstract

A new seven transistors (7T) dual threshold voltage SRAM cell is proposed in this paper for simultaneously reducing the active and standby mode power consumption while enhancing the data stability and the read speed. With the new 7T SRAM cell, the storage nodes are isolated from the bitlines during a read operation, thereby enhancing the data stability as compared to the standard six transistors (6T) SRAM circuits. The transistors of the cross-coupled inverters are not on the critical read delay path with the new technique. Minimum sized dual-threshold-voltage transistors are therefore conveniently used in the cross-coupled inverters for significantly reducing the leakage power consumption without causing a degradation in the read speed. With the proposed 7T SRAM circuit, the static noise margin and the read speed are enhanced by up to 87% and 17%, respectively, as compared to the conventional 6T SRAM circuits. Furthermore, the leakage and the write power consumptions of the proposed dual-V, SRAM circuit are reduced by up to 66% and 35%, respectively, as compared to the conventional 6T SRAM circuits in a 65 nm CMOS technology.