Low-power and low glitch area current steering DAC

Abstract

A 12-bit partial segmented current steering digital to analog converter (DAC) with low glitch area, power consumption, and integral nonlinearity (INL) error is proposed in this work. The cause of the glitch area and its possible solutions are explored. A current-mode logic (CML) latch with reduced output swing (Vdd to slightly below threshold voltage) is used at the input to the differential switch which reduces the glitch area (also known as glitch energy) significantly to 0.25 pVs. Further, this latch is used in the digital block of the proposed DAC to reduce the area and power requirement of the overall design. A dummy switch is used at the output of the differential switch to diminish effect of charge feedthrough at the output node of a current steering DAC. It also helps in the reduction of minimum allowable voltage headroom as compared to conventional double cascode structure and reduction of total power consumption to 9.1 mW operating at 200 MHz. The design and simulation of current steering DAC are performed in a 0.18 μm standard CMOS technology library using Cadence Virtuoso tool with a supply voltage of 1.8 V.