Abstract
This paper describes a 10 b 70 MHz CMOS digital-to-analog converter (DAC) for video applications. The proposed 10 b DAC is composed of a unit decoded matrix for 7 MSB's and a binary weighted array for 3 LSBs, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascode current sources and differential switches with the proposed new deglitching circuit improve dynamic performance. The fabricated and measured prototype DAC in a 0.8 um double-poly double-metal n-well CMOS process typically shows a spurious free dynamic range of 55 dB and a total harmonic distortion of -49 dB at a 3 V supply voltage and a 70 MHz update rate with a 120 mW power consumption. The measured differential and integral nonlinearities are /spl plusmn/0.69 LSB and /spl plusmn/0.79 LSB at a 10 b level, respectively.
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