Low Power and High Performance 8t SRAM Cell with Double Ended Bit Line Configuration for Improved Write Operation

Abstract

Objectives: To propose a new 8T SRAM architecture that uses two buffer transistors that help in faster discharging of bit line and boosts the cell performance by reducing its delay, power consumption and improving its write SNM. Methods/ Statistical Analysis: Parameters that we have taken in this design are power, delay and stability. Stability of the cell is determined with the help of static noise margin. For the simulation of the proposed and existing cell, Synopsys tool (C-Designer) and 90nm CMOS technology is used. Findings: We have done our analysis by varying the voltage. We have scale down the voltage from 1.8V to 0.5V. Maximum power reduction is observed in our proposed design. The power consumption of cell is significantly reduced to 0.175 μW as compared to 0.707 μW in standard 8T Static-RAM cell (keeping supply voltage as 1.2V). 8T Static-RAM cell proposed is 85% faster than the standard 8T Static-RAM. The stability of proposed Static-RAM cell is calculated using SNM. The read and write SNM values for the proposed cell is 301mV and 654mV respectively. Application: SRAMs have a wide range of applications for example handheld devices, portable appliances, Desktop, laptop, mobile phone etc. SRAM is used also in FPGAs and CPLDs.