Low power and compact architecture of sector transition reduction encoding technique

Abstract

Today's high-speed technologies are integrating many millions of transistors in a chip by the processes of the Deep-Submicron (DSM) fabrication. The trend leads to an increase in die size and a decrease in the horizontal dimensions of devices and interconnections. Power consumption is the dominating effect of the interconnections in DSM, is due to the continuous transition of data. Dynamic Sector (DS) transition reduction algorithm is a memory-based bus encoding coding technique, its working on the principle of divide the entire memory into sectors with help of sector heads. It saves dynamic power consumption up to 30 percent with the compact architecture of the design.