Abstract
A data decision and a static frequency divider in source coupled FET logic with a supply voltage of 1.5 V have been designed and fabricated. Both circuits, using 0.2 /spl mu/m gate length enhancement and depletion AlGaAs-GaAs HEMTs (f/sub T/=60/55 GHz), operate up to 20 Gbit/s and 17 GHz. The power consumption is 24 and 21 mW for the data decision circuit and the static frequency divider together with the output buffer, respectively.
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