Low pinch-off voltage f.e.t. logic (l.p.f.l.): I.s.i. oriented logic approach using quasinormally off GaAs m.e.s.f.e.t.s.

Abstract

A new l.s.i. oriented logic approach, low pinch-off voltage f.e.t. logic (l.p.f.l.), leading to highly versatile logic gates capable of combining high speed and low power consumption and requiring a standard fabrication process, is introduced and structures of complex logic gates realisable with this approach are described. Furthermore, a tentative comparison of the l.p.f.l. approach with other m.e.s.f.e.t. logic approaches to date is presented to show their respective design trade-offs which dictate the range of applications open to each of these approaches. The comparison is based on both computer simulations and experimental measurements on test circuits such as ring oscillators, flip-flops and binary frequency dividers.