Low Phase-Noise CMOS Quadrature Oscillator based on (N × 4)-stage Self-Timed Ring

Abstract

Quadrature phases with high frequency and low-phase noise are crucial in many applications. This paper deals with a low phase-noise quadrature phase generation based on self-timed ring oscillator (STRO). Quadrature phases can be generated simply by implementing 4-stage STRO and 1/N (−10 log(N) dB) phase noise enhancement can be obtained simply by implementing (N × 4)-stage STRO, while keeping the same oscillation frequency and the quadrature phase generation, at the cost of a higher power consumption. A 5 GHz (N × 4)-stage STROs has been simulated and 4-stage STRO has been fabricated in STMicroelectonics CMOS 65 nm. The power consumption is 1 mW with a 1.2 V supply. The measured phase noise at 10 MHz offset is −110 dBc/Hz resulting a figure of merit (FoM) of −164.5 dBc/Hz.